Srotas is AI-native Network-on-Chip IP for inference silicon. It routes with workload awareness, accelerates collective communication in the fabric itself, and ships with formal proofs of correctness — not just testbenches.
Others automate the design. Others optimize the plan. Srotas makes the fabric intelligent at runtime — and proves it.
Modern accelerators are no longer one chip running one model. They are chiplet systems serving many tenants and Mixture-of-Experts workloads at once — where traffic patterns shift every few microseconds. A fabric that was configured once, at design time, can't keep up. The interconnect, not the compute, is now the bottleneck.
Srotas is built around three structural differentiators — each one architectural, not incremental, and each one aimed squarely at AI inference silicon.
Compiler-emitted slack tags travel with the traffic, so the fabric knows which packets are latency-critical and which can wait. NIU-resident logic acts on that knowledge every cycle — no host in the loop, no design-time guesswork.
A concentrated mesh with MECS express channels makes one-to-many and reduction traffic first-class citizens. In-network reduction units collapse collective operations inside the fabric instead of bouncing them through memory.
Deadlock freedom, ordering, isolation — delivered as formal correctness proofs alongside the IP, born from a decade of design-verification practice. Your sign-off review starts from proofs, not from hope.
Srotas is a scalable mesh-based fabric with express channels for one-to-many traffic, workload-aware scheduling at the network interface, hardware-enforced isolation between tenants, and in-fabric acceleration of collective operations. It extends cleanly across chiplet boundaries and is developed with formal verification as a first-class deliverable. Detailed architecture documentation is available to licensees and partners under NDA.
Architecture decisions at SrotasSemi are settled by data, not opinion. Our containerized T3 toolchain evaluates every topology and routing choice end-to-end — from workload mapping to Pareto frontier.
Maps real AI workloads to the accelerator and extracts the traffic each layer actually generates.
Converts workload behaviour into fabric-level traffic demands — the ground truth for evaluation.
Cycle-accurate network simulation of candidate topologies and routing policies under that traffic.
Latency, throughput, and cost trade-offs visualised — so the frontier picks the architecture.
SrotasSemi is a fabless semiconductor IP company headquartered in Bengaluru, India — a city that houses a substantial share of the world's chip-design talent, yet almost none of the world's chip IP ownership. We exist to change that ratio.
The company was founded by a semiconductor engineer whose career spans Network-on-Chip architecture and design verification at Qualcomm, Tenstorrent, and Meta — the places where modern AI silicon interconnect was designed, broken, and fixed. That verification-first DNA is why Srotas ships proofs, not just RTL.
Whether you're architecting an AI accelerator, exploring chiplet interconnect, or backing India's semiconductor IP story — we'd like to hear from you.